1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more particularly, to an electrically erasable and programmable read only memory device (EEPROM) including a plurality of memory cell transistors each having a control gate and a floating gate.
2. Description of the Related Art
As well known in the art, each cell transistor employed in such an EEPROM is constructed such that a floating gate is formed over a channel region of a semiconductor substrate defined by source and drain regions with an intervening gate insulating film, and a control gate is formed on another gate insulating film covering the floating gate. By applying a certain voltage between the control gate and the drain region, carriers such as electrons are injected and extracted into and from the floating gate. The EEPROM of this type, however, requires a relatively complicated manufacturing process because of the formation of the control gate over the floating gate.
Therefore, such an EEPROM is disclosed in Japanese Patent Application Disclosure SHO No. 59-155968 that simplifies the manufacturing process. This EEPROM constitutes a control gate with a diffusion region.
Referring to FIGS. 10(A) and 10(B), each memory cell in such an EEPROM includes N.sup.+ -type impurity diffusion layers 23, 24, 25 and 26 selectively formed in a device formation region or an active region on a P-type single-crystal silicon substrate 21 which is partitioned or defined by a field oxide layer 22. This memory cell is composed of a cell transistor and a select transistor. The diffusion layer 23 serves as a source region of the cell transistor, and the diffusion layer 24 serves as a drain region of the cell transistor and further as a source region of the select transistor. The diffusion layer 25 operates as a drain region of the select transistor. This region 25 also serves as a bit line. The diffusion layer 26 serves as a control gate of the cell transistor. This region 26 is covered with a gate insulating film 28 made of silicon oxide, on which a floating gate 29 made of polysilicon is formed. The floating gate 29 is elongated over a gate insulating film 27 covering the channel region between the source region 23 and the drain region 24.
The channel region between the regions 24 and 25 for the select transistor is covered with a gate insulating film 30, over which a selector gate 31 for the select transistor crosses. Each of the floating gate 29 and the selector gate 31 may be formed simultaneously as a first level wiring layer of a multi-level wiring structure.
A silicon oxide layer 32 is formed over the entire surface by the so-called CVD method. Formed on the silicon oxide layer 32 in a horizontal direction in parallel to each other are an aluminum common line 34 connected to the source region 23 through a contact hole 33 and a bit line 36 made of aluminum connected to the bit line region 25 through a contact hole 35.
Although only one memory cell is shown in FIG. 10, the control gate region 26 is elongated to be employed in common for the adjacent cells, as shown in FIG. 11. Further, in order to reduce the resistance of the region 26, a wiring layer 37 is formed along the region 26 and connected thereto via contact holes 38. It is to be noted that, the wiring 37 is buried in the insulating layer 32 and made of polysilicon. The wiring layer 37 is further formed to cover the floating gates 29 via the silicon oxide layer 32.
Referring to FIG. 12, the memory cell thus constructed has a cell transistor Qm and a select transistor Qs. As is also apparent from the above description, the transistors Qm and Qs are connected to the word line WL.sub.i (31), the wiring line (CGi) 37, the common line (CL.sub.j) 34 and the bit line (BLj) 36.
An erasing operation for the above cell is performed by setting the drain region 24 to 0 volts and the control gate region 26 to a higher potential, to thereby inject electrons into the floating gate 29 by the Fowler-Nordheim (F-N) tunnel effect from the drain region 24. Conversely, a programming operation for the cell is performed by setting the control gate region 26 to 0 volts and the drain region 24 to a higher potential. The electrons are thus extracted from the floating gate 29 through the silicon oxide layer 27 by an F-N tunnel effect to the drain region. Thus, the injection and extractions of carriers are performed in this EEPROM, like the conventional EEPROM.
Here, representing the voltage between the drain region 24 and programming region 26 as V.sub.CG, the capacitance (of the section of the silicon oxide layer 27) between the floating gate 29 and the drain region 24 as C.sub.1, and the capacitance (of the section of the silicon oxide layer 28) between the floating gate 29 and the programming region 26 as C.sub.2, the potential of the floating gate FG is expressed as follows: EQU V.sub.FG =V.sub.CG .multidot.C.sub.2 /(C.sub.1 +C.sub.2) (1)
As is apparent from the operation (1), the voltage V.sub.FG may be increased by decreasing the capacitance C1, i.e., the facing area of the floating gate 29 and the drain region 24. The voltage needed for erasing and programming can be reduced accordingly. In other words, the EEPROM can operate on a reduced power voltage.
However, decreasing the facing area between the floating gate 29 and the drain region 24 of the cell transistor results in decrease in size of the cell transistor, so that the on-state current of the cell transistor is reduced to lower the operation speed.